Field
The present disclosure relates generally to flip-flop design, and more particularly, to flip-flop circuitry with improved scan hold-margin.
Background
In flip-flop circuits, the minimum setup time for a flip-flop is the minimum amount of time that a data signal needs to be held steady, e.g., held steady at a logic “0” or a logic “1” state, before a clock event, e.g., a rising edge of a clock signal, so that the data is reliably sampled by the clock on a synchronous input signal to the flip-flop. In flip-flop circuits, the minimum hold time is the minimum amount of time the data signal should be held steady, e.g., held steady at a logic “0” or a logic “1” state, after the clock event, e.g., a rising edge of a clock signal, so that the data are reliably sampled on a synchronous input signal to the flip-flop. Hold-margin is an indication of how close the actual hold time of a data signal is to the minimum hold time of the data signal.
In some semiconductor process technologies, it is becoming difficult to ensure there is enough hold-margin between launch and capture flip-flops. Ensuring that there is enough hold-margin between launch and capture flip-flops may be especially difficult for scan-paths that tend to have shallow logic depths, i.e., where the number of logic gates between an input of a logic function and an output of a logic function is small such that the delay through such logic gates is small relative to the hold-margin of the flip-flops.
The difficulty with ensuring that there is enough hold-margin between launch and capture flip-flops can be due to increased process variation from smaller geometries. The difficulty with ensuring that there is enough hold-margin between launch and capture flip-flops may be further aggravated by the fact that smaller technology/fin field effect transistor (FinFET) devices may be faster.
In FinFET technologies or other semiconductor process technologies, issues with hold-margin may lead to an increase in the number of buffers used. For example, some circuitry may have four times to five times more buffers as compared to earlier semiconductor process technologies. An increased number of buffers may be used to avoid hold violations. Increasing the number of buffers used to address issues with hold-margin, however, may increases area used on a semiconductor die, increase leakage current, increase dynamic power overhead, or some combination of these. Accordingly, addressing issues with hold-margin in a more area efficient way, a more power efficient way, or both may improve the flip-flop design.